SX1231 Calculator
Generic
Oscillator Frequency (MHz)
FSTEP
Use External Clock Instead of Crystal
Radio
Modulation
FSK
OOK
Carrier Frequency (MHz)
FSK Frequency Deviation (kHz)
Modulation Index, β=
Transmitter
Power Amplifier Selection
PA0 on pin RFIO
PA1 & PA2 on pin PA_BOOST
Output amplification
PA Ramp rise/full time
3.4 ms
2 ms
1 ms
500 us
250 us
125 us
100 us
62 us
50 us
40 us
31 us
25 us
20 us
15 us
12 us
10 us
Modulation Shaping
Enable Over-Current Protection
Max. Current (mA)
Receiver
LNA
LNA input impedance
50 Ohm
200 Ohm
LNA gain setting
Automatic
Max. Gain
Max. – 6 dB
Max. – 12 dB
Max. – 24 dB
Max. – 36 dB
Max. – 48 dB
Continuous Digital AGC
Enable Sensitivity Boost
Band Filter
Single Side Channel Bandwidth (kHz)
DC Cancelation cut-off Frequency
15.92 % of RxBw
7.96 % of RxBw
3.98 % of RxBw
1.99 % of RxBw
0.99 % of RxBw
0.50 % of RxBw
0.25 % of RxBw
0.12 % of RxBw
AFC
Single Side Channel Bandwidth for AFC (kHz)
AFC DC Cancelation cut-off Frequency
15.92 % of RxBw
7.96 % of RxBw
3.98 % of RxBw
1.99 % of RxBw
0.99 % of RxBw
0.50 % of RxBw
0.25 % of RxBw
0.12 % of RxBw
Auto Start AFC on RX
Clear error on AFC start
Optimize AFC for low modulation index
Low modulation index optimalization offset (Hz)
Demodulator
RSSI Threshold (dBm)
OOK Threshold Type
Fixed
Peak
Average
Threshold decay step
0.5 dB
1.0 dB
1.5 dB
2.0 dB
3.0 dB
4.0 dB
5.0 dB
6.0 dB
Threshold decay time
once per chip
once every 2 chips
once every 4 chips
once every 8 chips
twice in each chip
4 times in each chip
8 times in each chip
16 times in each chip
Threshold noise floor level (dB)
Threshold filter coefficient
f_C ≈ chip rate / (32 * π)
f_C ≈ chip rate / (8 * π)
f_C ≈ chip rate / (4 * π)
f_C ≈ chip rate / (2 * π)
Threshold level (dB)
Payload
Bit Rate (kbit/s)
Actual Bit Rate (bit/s)
Data Operation Mode
Packet Mode
Continuous Mode
Enable Bit Synchronizer
Packet Handeling
Packet Format
Preamble Length (Byte)
Enable Sync Word
Sync Word Length (Byte)
Sync Word
Sync Word max. bit errors
Packet Format
Fixed Length
Variable Length
Unlimited Length
Payload Message Length (Byte)
(excl. address byte)
Max. RX Payload Message Length (Byte)
(excl. length and address bytes)
Encoding
None
Manchester
Whitening
Enable CRC-16-CCITT checksum
(TX Only)
Do not clear FIFO on CRC error
Address Filtering
None
Node Address
Node + Broadcast Address
Node Address (0-255)
Broadcast Address (0-255)
Enable AES-128 Encryption
AES Key
Preamble
10
x '0xAA'
Sync. Word
0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01
Manchester
:
Payload:
Length
1-byte
Address
1-byte
Encrypted:
Message
upto 64
bytes
padding
upto 15
* '00'
CRC
2-byte
Packet structure
Packet Engine
FIFO Fill Condition
On SyncAddress interrupt
If FifoFillCondition is set
TX Start Condition
Fifo byte count > Fifo Threshold
Fifo byte count > 0
FifoLevel Interrupt Threshold
Inter-packet RX Delay
Auto Restart RX after InterPacketRxDelay
Auto Modes
Enable Auto Modes
Enter Condition
Rising edge of FifoNotEmpty
Rising edge of FifoLevel
Rising edge of CrcOk
Rising edge of PayloadReady
Rising edge of SyncAddress
Rising edge of PacketSent
Falling edge of FifoNotEmpty (i.e. FIFO empty)
Exit Condition
Falling edge of FifoNotEmpty (i.e. FIFO empty)
Rising edge of FifoLevel or Timeout
Rising edge of CrcOk or Timeout
Rising edge of PayloadReady or Timeout
Rising edge of SyncAddress or Timeout
Rising edge of PacketSent
Rising edge of Timeout
Intermediate Mode
Sleep mode (SLEEP)
Standby mode (STDBY)
Receiver mode (RX)
Transmitter mode (TX)
Digital I/O Pin Mapping
Clock Out
CLKOUT frequency
DIO0
Sleep
Stdby
FS
RX
TX
-
-
PllLock
SyncAddress
PllLock
-
-
-
Timeout
TxReady
LowBat
LowBat
LowBat
Rssi
LowBat
ModeReady
ModeReady
ModeReady
ModeReady
ModeReady
Sleep
Stdby
FS
RX
TX
-
-
-
CrcOk
PacketSent
-
-
-
PayloadReady
TxReady
LowBat
LowBat
LowBat
SyncAddress
LowBat
-
-
PllLock
Rssi
PllLock
DIO1
Sleep
Stdby
FS
RX
TX
-
-
-
Dclk
Dclk
-
-
-
RxReady
TxReady
LowBat
LowBat
LowBat
LowBat
LowBat
-
-
PllLock
SyncAddress
PllLock
Sleep
Stdby
FS
RX
TX
FifoLevel
FifoLevel
FifoLevel
FifoLevel
FifoLevel
FifoFull
FifoFull
FifoFull
FifoFull
FifoFull
FifoNotEmpty
FifoNotEmpty
FifoNotEmpty
FifoNotEmpty
FifoNotEmpty
-
-
PllLock
Timeout
PllLock
DIO2
Sleep
Stdby
FS
RX
TX
-
-
-
Data
Data
-
-
-
Data
Data
-
-
-
Data
Data
-
-
-
Data
Data
Sleep
Stdby
FS
RX
TX
FifoNotEmpty
FifoNotEmpty
FifoNotEmpty
FifoNotEmpty
FifoNotEmpty
-
-
-
Data
Data
LowBat
LowBat
LowBat
LowBat
LowBat
AutoMode
AutoMode
AutoMode
AutoMode
AutoMode
DIO3
Sleep
Stdby
FS
RX
TX
-
-
-
Rssi
TxReady
-
-
-
RxReady
TxReady
AutoMode
AutoMode
AutoMode
AutoMode
AutoMode
-
-
-
Timeout
TxReady
Sleep
Stdby
FS
RX
TX
FifoFull
FifoFull
FifoFull
FifoFull
FifoFull
-
-
-
Rssi
TxReady
LowBat
LowBat
LowBat
SyncAddress
LowBat
-
-
PllLock
PllLock
PllLock
DIO4
Sleep
Stdby
FS
RX
TX
-
-
-
Timeout
TxReady
-
-
-
RxReady
TxReady
LowBat
LowBat
LowBat
SyncAddress
LowBat
-
-
PllLock
PllLock
PllLock
Sleep
Stdby
FS
RX
TX
-
-
-
Timeout
ModeReady
-
-
-
Rssi
TxReady
LowBat
LowBat
LowBat
RxReady
LowBat
-
-
PllLock
PllLock
PllLock
DIO5
Sleep
Stdby
FS
RX
TX
-
ClkOut
ClkOut
ClkOut
ClkOut
-
-
-
Rssi
ClkOut
LowBat
LowBat
LowBat
LowBat
LowBat
ModeReady
ModeReady
ModeReady
ModeReady
ModeReady
Sleep
Stdby
FS
RX
TX
-
ClkOut
ClkOut
ClkOut
ClkOut
-
-
-
Data
Data
LowBat
LowBat
LowBat
LowBat
LowBat
ModeReady
ModeReady
ModeReady
ModeReady
ModeReady
Startup Timing
Spectrum
Your browser does not support inline SVG.
Legend:
= Filtered by RX filter
= Filtered by AFC filter
Artist impression of power spectral density.
(NOTE: This is in no way a complete or accurate simulation of the PSD.)
Register values
Export
Import
Addr
Value
Prev.
POR
©
License: MIT | Copyright 2019 David Imhoff | Version: 0.1